The present invention is related to the fabrication of wafer stacks. More particularly, the present invention is related to the fabrication of wafer stacks using solder to adjoin adjacent metalized trenches.
Since the development of integrated circuit technology, computers and computer storage devices have been made from wafers of semiconductor material comprising a plurality of integrated circuits. After a wafer is made, the circuits are typically separated from each other by dicing the wafer into individual chips. Thereafter, the individual chips may be bonded to carriers of various types, interconnected by wires and packaged. However, such two-dimensional packages of chips may fail to optimize the number of circuits that may be fabricated in a given space, and may also introduce undesirable signal delays, capacitance, and inductance as signals travel between chips.
Recently, three-dimensional stacks of single chips have emerged as an important packaging approach. A typical multi-chip electronic module may include multiple individual integrated circuit chips adhesively secured together as a monolithic structure (i.e., a xe2x80x9cwafer stackxe2x80x9d) extending in one direction as a single row or column. Each of the individual wafers may be electrically coupled to an adjacent wafer through electrical connections. One problem with the formation of wafer stacks is how to make proper and complete electrical connections between the respective layers of the wafer stack.